CXD1968AR
ADC_CONTROL
Read/Write
RESET: 0xA2
Default R/W
Offset Address: 0xB9
Bit
7
Name
REFPD_Q
STDBY_Q
RESET_Q
PWRDN_Q
REFPD_I
STDBY_I
RESET_I
PWRDN_I
Description
Set to “1” to power down reference in Q channel ADC.
Set to “1” to put the Q channel ADC in standby mode.
Q channel ADC is reset by writing a “0” or “1” sequence to this bit.
Set to “1” to power down the Q channel ADC.
1
0
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
3
Set to “1” to power down reference in I channel ADC.
Set to “1” to put the ADC_I in standby mode.
2
1
I channel ADC is reset by writing a “0” or “1” sequence to this bit.
Set to “1” to power down the I channel ADC.
0
Note) 1. Both ADCs are reset on power-up.
2. Before powering-down an ADC, ensure its respective reference is first powered-down.
ADC_CONTROL2
Read/Write
RESET: 0x47
Default R/W
Offset Address: 0xBA
Bit
Name
Description
Selects reference voltage on ADC_I and ADC_Q.
00: refout = 0.35V → 0.7V full scale diff p-p input
01: refout = 0.50V → 1.0V full scale diff p-p input
10: refout = 0.75V → 1.5V full scale diff p-p input
11: refout = 1.00V → 2.0V full scale diff p-p input
7:6 REFSEL[1:0]
01
R/W
External A/D select.
5
4
Ext_A/D_Select
0
0
R/W
R/W
0: Internal A/D selected
1: External A/D selected
Selects internal ADC output type.
ADC_Offset_2s_Comp
0: Offset binary: default for the CXD1968AR
1: 2’s complement
Used for testing ADC.
3
2
ADC_test_mode
DCCEN
0
1
R/W
R/W
0: Normal mode
1: Test mode
Enables ADC clock duty cycle correction.
Sets pk-pk level of ADC sampling clock on ADC_I and
ADC_Q.
1
0
CLKRCVEN
1
1
R/W
0: 3.3V CMOS input level
1: 1.2V CMOS input level
Enables driving of the ADC clock directly from XTALI
input.
ADC_DIRECT_CLKEN
0: Normal mode (ADC clocked from PLL)
1: Direct clock mode
Note) When using external A/D, the direct clock mode must be used.
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SONY [ SONY CORPORATION ]
