CXD1968AR
PLL_F
Read/Write
RESET: 0x52
Default R/W
Offset Address: 0xA8
Bit
Name
Description
PLL feedback divider bits 7 to 0.
FVCO = FREF × NF – Valid range is 200MHz to 400MHz.
NF = 2 × (128 × F7 + 64 × F6 + 32 × F5 + 16 × F4 + 8 × F3
+ 4 × F2 + 2 × F1 + F0)
7:0 F[7:0]
52h
R/W
Default value for F[7:0] is 0x52. Yielding a value of 164 for NF.
The above register defaults are for 4MHz crystal operation.
The table below shows the suggested PLL settings when using other crystal frequencies.
Xtal Freq [MHz]
4.00
OD[1:0]
R[4:0]
F[7:0]
PLL_FODR
0x62
PLL_F
0x52
0x52
0x52
0x50
3
3
3
3
2
82 decimal
82 decimal
82 decimal
80 decimal
8.00
4
8
0x64
16.00
0x68
20.48
10 decimal
0x6A
PLL_CONTROL
Read/Write
RESET: 0x40
Default R/W
Offset Address: 0xA9
Bit
7
Name
Reserved
Description
0
1
0
R/W
R/W
R/W
6
PLL_power_down
PLL_op_enable
1: Power down the PLL.
1: Enable the PLL output clocks.
5
1: Bypass the PLL generated clock and use external clock
source.
4
PLL_bypass
0
R/W
3
2
1
0
ext_clk_enable
PLL_op_invert
PLL_test_mode
clock_disable
1: Enables the external fast clock (instead of the PLL).
1: Inverts the PLL output clocks.
0
0
0
0
R/W
R/W
R/W
R/W
1: Puts the PLL in test mode.
1: Disables most of the clocks (for low noise ADC evaluation).
TUNER_CTRL5
Read/Write
Description
RESET: 0x00
Offset Address: 0xAF
Bit
7
Name
Default R/W
0
0: Tuner Quiet I2C bus disabled.
1: Tuner Quiet I2C bus enabled.
enable_quiet_I2C
6
5
4
Reserved
Reserved
Reserved
0
0
0
NB: Do not set to “1”.
3:2 Reserved
00
0
R/W
R/W
R/W
1
0
Reserved
Reserved
NB: Do not set to “1”.
NB: Do not set to “1”.
0
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SONY [ SONY CORPORATION ]
