CXD1968AR
SMOOTH_DP0
Read/Write
RESET: 0x80
Default R/W
Offset Address: 0xB7
Bit
Name
Description
This part of the data period value represents the fractional
number of clock periods per TS word.
A read from the SMOOTH_DP0 register returns the current
value of the fractional part of the data period value.
A read from SMOOTH_DP0 also causes the current value
of the integer part of the data period value to be stored in a
holding register, which can be accessed by reading from
SMOOTH_DP1.
Writing to SMOOTH_DP0 only has an effect when the
DATA_PERIOD_AUTO bit of the SMOOTH_CTRL register
is set to “0”. In this case, writing to SMOOTH_DP0 has the
effect of storing the 8-bit value in a holding register. Writing
to SMOOTH_DP1 then has the effect of transferring data
from the holding register to the SMOOTH_DP0 register
proper.
7:0 DATA_PERIOD[7:0]
80h
R/W
For these reasons SMOOTH_DP0 and SMOOTH_DP1
should be read from or written to in order, SMOOTH_DP0
first.
SMOOTH_DP1
Read/Write
Description
RESET: 0x09
Default R/W
Offset Address: 0xB8
Bit
Name
This part of the data period value represents the integer
number of clock periods per TS word.
A read from the SMOOTH_DP1 register returns the integer
part of the data period value previously stored in a holding
register when a read from the SMOOTH_DP0 register
occurred (see SMOOTH_DP0 above).
Writing to SMOOTH_DP1 only has an effect when the
DATA_PERIOD_AUTO bit of the SMOOTH_CTRL
register is set to “0”. In this case, writing to SMOOTH_DP1
has the expected effect of updating the SMOOTH_DP1
register value, and has the additional effect of transferring
data from a holding register (updated during a
7:0 DATA_PERIOD[15:8]
09h
R/W
SMOOTH_DP0 write operation) into the SMOOTH_DP0
register (see SMOOTH_DP0 above).
- 93 -
SONY [ SONY CORPORATION ]
