CXD1968AR
INTERRUPT_MASK
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0xA4
Bit
7
Name
Ts_if_int_En
Cofdm_Int_En
Description
1: Enable TS interface interrupts.
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
1: Enable COFDM demodulator core interrupts.
5
Ts_synch_Lock_En 1: Enable TS lock interrupt.
4
Ts_Llck_Flag_En
Reserved
1: Enable TS lost lock interrupt.
3
2
Ber_Es_En
1: Enable second error interrupt.
1
Ber_Ses_En
1: Enable second severity error interrupt.
0
Rs_cwrjct_Flag_En 1: Enable codeword reject interrupt.
TIMEOUT_VAL
Read/Write
RESET: 0xFF
Default R/W
Offset Address: 0xA6
Bit
Name
Description
Sets the time after which the CXD1968AR will timeout an
I2C access when waiting for an I2C master response. The
timeout period can be set to between approximately 2 and
500ms represented by 00h and FFh in this register.
7:0 TIMEOUT_VAL[7:0]
FFh
R/W
PLL_FODR
Read/Write
Description
RESET: 0x62
Default R/W
Offset Address: 0xA7
Bit
7
Name
Reserved
0
R/W
00: Not allowed
01: 1
PLL output divider.
Default value for OD[1:0] is 03h.
6:5 OD[1:0]
4:0 R[4:0]
11
R/W
10: 2
Yielding a value of 4 for NO.
11: 4
PLL input divider. Controls comparison frequency FREF.
FREF = FIN / NR – Valid range is 2MHz to 8MHz.
NR = 16 × R4 + 8 × R3 + 4 × R2 + 2 × R1 + R0
00010 R/W
Default value for R[4:0] is 0x02. Yielding a value of 2 for NR.
Note) PLL output frequency FOUT = (FIN × NF / (NR × NO)
Where FIN is the frequency of the clock signal present on the XTALI pin.
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SONY [ SONY CORPORATION ]
