CXD1968AR
Miscellaneous Registers
CHIP_INFO
Read Only
RESET: 0x61
Default R/W
Offset Address: 0xA0
Bit
Name
Description
Chip identification number
Chip version number
7:2 CHIP Ident
1:0 Version
011000
01
R
R
Note) This register cannot be read back until the PLL has been enabled.
RST_REG
Read/Write
RESET: 0x04
Default R/W
Offset Address: 0xA2
Bit
Name
Description
ADC reset enable.
7
adc_rst
0
R/W
1: Enable ADC reset when cold reset is active.
COFDM demodulator core reset enable.
6
5
cofdm_rst
Vit_rst
0
R/W
1: Enable COFDM demodulator reset when warm or cold
reset is active.
Viterbi reset enable.
0
0
R/W
R/W
1: Enable Viterbi reset when warm or cold reset is active or
when the auto recovery mode is selected.
FEC (excluding Viterbi) reset.
1: Enable FEC (excluding Viterbi) reset when warm or cold
reset is active or when the auto recovery mode is
selected.
4
fec_rst
3
2
Reserved
Hard
0
1
R/W
R/W
Set when RESETN pin of device is driven active.
0: Release after power-on reset (after PLL is stable)
1: No effect
1
0
Cold
Cold reset.
1: Reset
1: Reset
0
0
R/W
R/W
Warm
Warm reset.
Note) Software must wait 500μs for the PLL to stabilize before setting RST_REG bit 2.
INTERRUPT_SOURCE
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0xA3
Bit
7
Name
Ts_if_int
Description
1: TS smoothing buffer overflow or underflow detected.
1: COFDM demodulator core Interrupt.
1: Transport stream locked.
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
Cofdm_Int
5
Ts_synch_Lock
Ts_Llck_Flag
Reserved
4
1: Transport stream lock lost.
3
2
Ber_Es
1: Errored second detected.
1
Ber_Ses
1: Severely errored second detected.
1: More than 8 error bytes in current packet.
0
Rs_cwrjct_Flag
Note) Each bit may be cleared by writing a “1” to the appropriate bit location.
- 88 -
SONY [ SONY CORPORATION ]
