CXD1968AR
AUTO_RESET
Read/Write
RESET: 0x01
Default R/W
Offset Address: 0xB1
Bit
7:1 Reserved
Disable
Name
Description
00h
1
R/W
R/W
0
1: Disable auto reset of the FEC on code rate change.
Read/Write
RF_IFAGC_CTRL0
RESET: 0x11
Default R/W
Offset Address: 0xB2
Bit
Name
Description
7:6 RF_IFAGCQ_PWM
RF_AGC_PWM bits 1:0
00
0
R/W
R/W
5
4
Reserved
0: IF_AGC is tri-state.
1: IF_AGC is driven.
IF_AGC_EN
1
R/W
00: Tri-state mode – RF_IFAGC_Q is a GPI pin.
01: Manual PWM mode for RF_IFAGC_Q output
10: GPO mode for RF_IFAGC_Q output set by bit 1 this reg
11: ZIF mode: Automatic PWM mode for Q channel AGC o/p
3:2 RF_IFAGCQ_MODE
00
0: RF_IFAGC_Q output 0 when GPO mode selected
1: RF_IFAGC_Q output 1 when GPO mode selected
1
0
RF_IFAGCQ_GPO
RF_IFAGCQ_GPI
0
1
R/W
R
Senses state of RF_IFAGC_Q input pin level.
0: RF_IFAGC_Q input at logic 0
1: RF_IFAGC_Q input at logic 1
RF_IFAGCQ_CTRL1
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0xB3
Bit
Name
Description
7:0 RF_IFAGCQ_PWM
RF_AGC_PWM bits 9:2
00h
R/W
Note) 1. In the time interval between host writes to RF_IFAGCQ_CTRL0 and RF_IFAGCQ_CTRL1, the
manual control to the AGC will have an intermediate value.
2. The ability to use the RFAGC output as a PWM output or a GPIO has been added to the
CXD1968AR compared to the CXD1973Q. RF_AGC_CTRL0[2:1] that were previously reserved
bits are now used for this purpose.
3. RF_IFAGCQ_PWM is a straight binary value.
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SONY [ SONY CORPORATION ]
