CXD1968AR
BDI_CTL
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x25
Bit
Name
Description
7:2 Reserved
00h
R/W
R/W
R/W
0: HP data and code rate
1: LP data and code rate
Selects priority of data for output
to the FEC.
1
0
BDI LPSelect
Reserved
0
NB: Do not set this bit to “1”.
0
DMP_CTL
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x26
Bit
Name
Description
7:1 Reserved
00h
0
R/W
R/W
0
DMP Disable CSI Weight
Set to disable soft decision weighting by CSI.
TPS_RCVD_1
Read Only
Description
Offset Address: 0x27
Bit
7
Name
Default R/W
Reserved
—
—
R
R
Set when an update to TPS_RCVD_2, 3, 4 caused the
data contents of the registers to change.
6
5
TPS RCVD Changed Flag
Set if the BCH check on the TPS data of the previous
frame was correct. This bit is NOT influenced by
TPS_CTL (TPS Use BCH).
TPS RCVD BCHOK Flag
TPS RCVD Sync Flag
—
—
R
R
Set if a TPS sync sequence was received. If the control
state machine is in MONITOR_TPS, then this bit
indicates presence/absence of a sync sequence in the
previous frame (updated every time a new TPS frame
is received).
4
If the control state machine is NOT in MONITOR_TPS
then this bit asserts as soon as a sync sequence is
detected, deasserting if the BCH check subsequently
fails.
3:2 Reserved
—
—
R
R
Frame number (within super-frame) indicated by TPS
data received in the previous frame.
1:0 TPSRCVFrame
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SONY [ SONY CORPORATION ]
