CXD1968AR
TPS_SET_2
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x2E
Bit
7
Name
Reserved
Description
0
R/W
000: Non hierarchical
001: α = 1
010: α = 2
011: α = 4
Hierarchy information for
current scheme
6:4 TPSSETHierarchy
000
R/W
100 to 111: Reserved
3:2 Reserved
00
00
R/W
R/W
00: QPSK
01: QAM-16
10: QAM-64
11: Reserved
Constellation for current
modulation scheme
1:0 TPSSETConstellation
Note) 1. Data in this register corresponds to the actual parameters used by the core.
2. This register is updated (If TPS_CTL -TPS Disable Update is NOT set) from TPS_RCVD_2 when
TPSSETFrame transitions from “3” to “0” (super-frame). Notice that the timing of the update does
not coincide with updates to the TPS_RCVD_2 register.
3. With the control state machine in IDLE, writes to TPS_SET_2 take immediate effect. Otherwise,
setting by the host takes effect at the beginning of the next super-frame. Only then will the
register read-back the data written by the host.
TPS_SET_3
Read/Write
RESET: 0x00
Offset Address: 0x2F
Bit
7
Name
Reserved
Description
Default R/W
0
000: 1/2
001: 2/3
010: 3/4
011: 5/6
100: 7/8
6:4 TPSSETLPCode
Low priority stream code rate
000
0
R/W
R/W
R/W
101 to 111: Reserved
3
Reserved
000: 1/2
001: 2/3
010: 3/4
011: 5/6
2:0 TPSSETHPCode
High priority stream code rate
000
100: 7/8
101 to 111: Reserved
Note) 1. Data in this register corresponds to the actual parameters used by the core.
2. This register is updated (If TPS_CTL -TPS Disable Update is NOT set) from TPS_RCVD_3 when
TPSSETFrame transitions from “3” to “0” (super-frame). Notice that the timing of the update does
not coincide with updates to the TPS_RCVD_3 register.
3. With the control state machine in IDLE, writes to TPS_SET_3 take immediate effect. Otherwise,
setting by the host takes effect at the beginning of the next super-frame. Only then will the
register read-back the data written by the host.
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SONY [ SONY CORPORATION ]
