CXD1968AR
TPS_RESERVED_1_ODD
Read Only
Offset Address: 0x2B
Bit
Name
Description
Default R/W
TPS reserved bits S40-S47 representing Cell-ID bits 15:8
respectively, received in TPS frame numbers 1 and 3.
7:0 CELLID[15:8]
—
R
TPS_RESERVED_2_ODD
Read Only
Description
Offset Address: 0x2C
Bit
Name
Default R/W
7:6 Reserved
TPS reserved bit S48 – DVB-H time sliced data present
in received data. In hierarchical mode, these bits
correspond to HP stream.
5
4
TimeSliced Data
MPE-FECData
—
R
TPS reserved bit S49 – DVB-H MPE-FEC encoded
data present in received data. In hierarchical mode,
these bits correspond to HP stream.
—
—
R
R
TPS reserved bits S50-S53 received during TPS frame
numbers 1 and 3.
3:0 TPS_RESERVED_ODD
TPS_SET_1
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x2D
Bit
Name
Description
7:2 Reserved
00h
R/W
Current frame number within super-frame as maintained by
internal counters.
The frame number is required to determine super-frame
boundaries (for TPS_SET_x updates).
The frame counter is initialized to the first received TPS frame
data (TPSRCVFrame), i.e., TPS data received while the control
state machine is in the WAIT_TPS state.
1:0 TPSSETFrame
00
R/W
The symbol counter increments at end of FFT processing. The
frame counter increments when the symbol counter wraps from
67 to 0.
With the control state machine in IDLE, writes to TPS_SET_1
take immediate effect. Otherwise, setting by the host takes effect
at the beginning of the next frame (when FFT output symbol
number wraps from 67 to 0). Only then will the register read-back
the data written by the host.
- 64 -
SONY [ SONY CORPORATION ]
