CXD1968AR
TPS_CTL
Read/Write
RESET: 0x04
Default R/W
Offset Address: 0x30
Bit
Name
Description
7:3 Reserved
00h
R/W
By default, TPS_SET_2, 3 registers are updated from
TPS_RCVD_2, 3 when TPSSetFrame transitions from “3” to
“0” (super-frame). If this bit is set, then the FIRST acceptable
TPS RCVD data (while state-machine is in WAIT_TPS) is
loaded into the TPS_SET_2, 3 registers irrespective of TPS
RCVD Frame number. This could assist faster acquisition,
except in the superframe immediately prior to a parameter
change.
Use First TPS
Immediately
2
1
R/W
By default, TPS RCVD and TPS SET registers are updated
only if the BCH check is OK (“good TPS”). When TPS Ignore
BCH is set both TPS_RCVD and TPS_SET registers are
updated irrespective of the BCH check.
1
0
TPS Ignore BCH
0
0
R/W
R/W
TPS Disable
Update
When set, this bit disables updating of the “SET” TPS data
from “RCVD” TPS data in the data stream.
CTL_FFTOSNUM
Read Only
Description
Offset Address: 0x31
Bit
7
Name
Reserved
Default R/W
—
R
FFT output symbol number counter (0...63). This counter
increments every symbol when new symbol data is available
at the output of the FFT.
6:0 CTL FFTOSNUM
—
R
A value of 127 read from this register implies that the counter
is not yet running (symbol number is not valid).
PIR_CTL
Read/Write
Description
RESET: 0x00
Default R/W
Offset Address: 0x34
Bit
Name
7:1 Reserved
00h
R/W
AGC_GAIN, TRL_TIMEOFF, CRL_FREQOFF and
BER_ESTIMATE are fields more than 8 bits which are each
accommodated in more than one register. It is therefore
possible for the field value to change in the time between the
two reads from the register pair. When a “1” is written to the
freeze bit (whether it was previously “0” or not), the field values
are latched. With the freeze bit “0” the data within the fields
changes dynamically.
0
Freeze
0
R/W
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SONY [ SONY CORPORATION ]
