CXD1968AR
Channel Bandwidth
The channel bandwidth is set indirectly by programming the TRL_NOMINALRATE_0, 1, 2 registers.
TRLNOMINALRATE has changed from a 16-bit number on the CXD1976R to a 24-bit number on the
CXD1968AR. These registers set the nominal rate of the sample timing NCO. TRL nominal rate is the ratio
of the FFT time sample clock to the (fixed) ADC clock frequency. The following formula should be used to
determine the TRLNOMINALRATE value:
16 × ChanBW
24
--------------------------------------
TRLNOMINALRATE =
× (2 )
FADC × 7
Note that the maximum allowable value of this register is 16777215 and the minimum is 11184811. Some
common settings are given below, calculated for 20.48MHz and 20.5MHz clocks:
Channel bandwidth
8MHz
FADC = 20.48MHz
14979657 (E49249h)
13107200 (C80000h)
11234743 (AB6DB7h)
FADC = 20.5MHz
14965043 (E45933h)
13094412 (C7CE0Ch)
11223782 (AB42E6h)
7MHz
6MHz
Example: 0xD8 0x65 0x49 ; write TRL_NOMINALRATE in three bytes
0xD8 0x1B 0x92 ; for 8MHz RF channel
0xD8 0x1C 0xE4 ; and 20.480MHz clock
Note) Error in the calculation of TRLNOMINALRATE more than 50ppm may compromise acquisition of 8K
transmissions.
Using Other IF Input Frequencies
IF signals outside the range 4.50MHz to 4.57MHz and 36.000MHz to 36.1667MHz are not recommended.
IF AGC Sense
The IF AGC sense is programed by setting the AGC_neg bit in the AGC_CTL register. When set the AGC
level output decreases when a larger signal is required, otherwise the AGC level output increases when a
larger signal is required.
Most tuners will not require this bit setting, so the register may not need to be programed.
Spectrum Inversion
The spectrum can be inverted to allow a reversed frequency spectrum from the tuner by setting the ITB
invert spectrum bit in the ITB_CTL register.
This may be required for operation with dual-conversion and Low IF architecture tuners.
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SONY [ SONY CORPORATION ]
