CXD1968AR
COFDM Demodulator Configuration
While there are many registers which can be programed to configure the COFDM demodulator, there are only
a few which must be programed to setup the interface to the tuner. The following must be configured:
Configure clock, PLL and ADC
Set ITB frequency for chosen IF frequency
Set TRL nominal rate for current channel bandwidth
IF AGC sense if required
Input spectrum inversion if required
Clock, PLL and ADC Configuration
This means setting the clock mode for operation using the internal oscillator (crystal) or from an external
clock source (tuner). PLL divider settings according to the oscillator or clock frequency. The ADC powers-
up in dual channel mode (defaults to ZIF input), for IF mode the unused Q channel is then turned-off.
A description has been given in section 2, PLL Operation, with reference to the application note EAN-0066
which includes code samples. Standard operation is described here with a 20.48MHz crystal.
Example: 0xD8 0xA7 0x6A ; PLL comparison frequency and input divider
0xD8 0xA8 0x50
0xD8 0xA9 0x00
wait 500μs minimum
0xD8 0xA9 0x20
0xD8 0xA2 0x00
0xD8 0xBA 0x43
; set PLL feedback divider
; power up the PLL
; PLL settling time
; enable PLL output
; clear hard reset
; enable clocking from the crystal
0xD8 0xB9 0xB2 ; power down ADC_Q
Signal IF Frequency
The ADC input IF frequency is programed via the ITB_FREQ_1, 2 registers. These make up a 14-bit value
– ITB frequency (IF-To-Baseband). This value is calculated using the following formula:
–1 × FIF
FADC
--------------------
ITBFREQ =
× 16384
If the IF is being undersampled (as will be the case with a High IF signal input) then FIF is the subsampled
IF, thus for a 36.1667MHz IF a derived value of 4.79MHz should be used in the equation
(2 × 20.480MHz – 36.1667MHz = 4.79MHz):
IF mode
Low
IF [MHz]
4.57
FIF [MHz]
4.57
FADC [MHz]
20.48
ITBFREQ
–3657 (31B7h)
–3968 (3080h)
–3868 (30E4h)
–3835 (3105h)
–3863 (30E9h)
–3996 (3064h)
High
High
High
High
High
36.00
4.96
20.48
36.125
36.1667
36.1667
36.00
4.835
4.7933
4.8333
5.00
20.48
20.48
20.50
20.50
Example: 0xD8 0x0C 0x05 ; write ITBFREQ in two bytes for
0xD8 0x0D 0x31 ; 36.1667MHz IF and 20.48MHz clock
It is important that the ITB frequency should be calculated using the correct ADC clock frequency.
Note) The spectrum invert bit in register ITB_CTL 0x0B may need to be set for Low IF operation, this may
also depend upon the tuner.
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SONY [ SONY CORPORATION ]
