CXD1968AR
Transport Stream Outputs
Transport stream data is output on the TSDATA outputs; it is clocked by the TSCLK output. The TSSYNC
output is active during the first byte of a TS packet. The TSVALID output can be used to indicate valid data.
The TSERR output indicates a TS packet containing uncorrected errors. The TSLOCK output is set active high
when a valid transport stream is locked on to.
Enabling/Disabling the Transport Stream Output
The transport stream outputs are enabled by setting the Tri_State_Outputs bit in the FEC_PARAMS register.
Serial/Parallel Data Output Selection
The default transport stream output mode is parallel. A serial output can be selected by resetting the
TS_parallel_sel bit in the FEC_PARAMS register.
Other Transport Stream Output Format Options
The default output format is as below:
In parallel mode, the MSB is output on the TSDATA7 pin, the LSB on TSDATA0. In serial mode, the MSB
is output first and the LSB last all on TSDATA0.
Data should be sampled on the rising edge of TSCLK.
TSVALID, TSSYNC and TSERR are all active high.
TSVALID active high indicates a valid data.
TSERR is active for the first 188 bytes if that packet contains an uncorrected error.
TSCLK is gated so that edges occur when TSVALID is active.
The following options are available and can be selected by programming the FEC_PARAMS and
BB_PARAMS registers:
In parallel mode, the MSB can be output on TSDATA0 and the LSB on TSDATA7, and in serial mode
the LSB can be output first and the MSB last by setting the Output_Sel_MSB bit in the FEC_PARAMS
register.
In serial mode, data can be output on TSDATA7 by setting the Ser_data-on_MSB bit in the
FEC_PARAMS register.
TSVALID, TSSYNC and TSERR can all be set active low by resetting the TSvalid_active_high,
TSsync_active_high and TSerr_active_high bits respectively in the BB_PARAMS register.
In parallel mode, the TSVALID output can be set to be active only during the first byte of a packet by
setting the TSvalid_pulse bit in the BB_PARAMS register.
TSERR can be set to be active only during the first byte (or bit in serial mode) by setting the TSerr_pulse
bit in the BB_PARAMS register. If this bit is reset, then TSERR can be set to be active until the start of
the next non errored TS packet by setting the TSerr_full bit in the BB_PARAMS register.
TSCLK can be set to be active continuously by setting the TSclk_full bit in the BB_PARAMS register.
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SONY [ SONY CORPORATION ]
