CXD1968AR
Transport Stream Smoothing
COFDM demodulation is naturally bursty. The demodulator operates on whole symbols of data at a time.
A whole symbol must be stored before FFT processing can begin. Transformed data is read out of the FFT
block as fast as possible into the following circuitry, resulting in a bursty TS. This bursty TS output can be
smoothed by the on-chip TS smoothing buffer.
The TS smoothing buffer is enabled by setting the ENABLE bit in the SMOOTH_CTRL register. The
smoothing buffer can operate in an automatic or manual mode.
Automatic Mode
In automatic mode, the smoothing buffer applies the correct degree of smoothing for the COFDM signal
being demodulated. Automatic mode is set by setting the DATA_PERIOD_AUTO bit in the
SMOOTH_CTRL register. The channel bandwidth must also be programed into the SMOOTH_CTRL
register using the CHANNEL_WIDTH bits.
Example: 0xD8 0xB4 0x03 ; enable automatic mode for 8MHz channel
Manual Mode
In manual mode, the degree of smoothing must be programed into the SMOOTH_DP1, 0 registers. The
SMOOTH_DP0 register bits represent the fractional number of clock periods per TS word. A read from
the SMOOTH_DP0 register returns the current value of the fractional part of the data period value.
A read from SMOOTH_DP0 also causes the current value of the integer part of the data period value
to be stored in a holding register, which can be accessed by reading from SMOOTH_DP1. For this
reason it is recommended that SMOOTH_DP0 and SMOOTH_DP1 are read as a pair of registers,
SMOOTH_DP0 first, followed by SMOOTH_DP1.
Writing to SMOOTH_DP0 only has an effect when the DATA_PERIOD_AUTO bit of the
SMOOTH_CTRL register is set to “0”. In this case, writing to SMOOTH_DP0 has the effect of storing
the 8-bit value in a holding register. Writing to SMOOTH_DP1 then has the effect of transferring data
from the holding register to the SMOOTH_DP0 register proper. As with read accesses, it is
recommended that write accesses to SMOOTH_DP0 and SMOOTH_DP1 are performed in pairs,
SMOOTH_DP0 first, followed by SMOOTH_DP1.
The SMOOTH_DP0 register bits represent the integer number of clock periods per TS word. A read
from the SMOOTH_DP1 register returns the integer part of the data period value previously stored in
a holding register when a read from the SMOOTH_DP0 register occurred (see SMOOTH_DP0 above).
Writing to SMOOTH_DP1 only has an effect when the DATA_PERIOD_AUTO bit of the
SMOOTH_CTRL register is set to “0”. In this case, writing to SMOOTH_DP1 has the expected effect
of updating the SMOOTH_DP1 register value, and has the additional effect of transferring data from a
holding register (updated during a SMOOTH_DP0 write operation) into the SMOOTH_DP0 register
(see SMOOTH_DP0 above).
Monitoring the Smoothing Buffer Status
The status of the smoothing buffer can be monitored by reading the SMOOTH_STAT register.
The UNDERFLOW flag is set when an underflow condition has been detected. An underflow condition
is where data is requested but cannot be provided because the read FIFO is empty. Note that when
data is requested but cannot be provided because the next TS word is a sync and at the same time the
SRAM FIFO does not contain a complete TS packet, this is part of the smoothing circuit's normal
operation and is not classed as an underflow condition. Write a “1” to this bit location to clear this bit.
Writing a “0” to this bit has no effect.
The OVERFLOW flag is set when an overflow condition has been detected. Write a “1” to this bit
location to clear this bit. Writing a “0” to this bit has no effect.
Example: 0xD8 0xB5 0x03 ; to clear smoothing buffer status flags
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SONY [ SONY CORPORATION ]
