CXD1968AR
Tuner Quiet I2C Interface
The tuner I2C interface allows the I2C interface to the tuner to be isolated from the host I2C interface to the rest
of the system. This uses on-chip switching.
When an I2C master wants to send data to the tuner, it must first enable the slave interface before sending the
data. To enable the tuner Quiet I2C interface the enable_quiet_I2C bit must be set in the TUNER_CTRL5
register (bit 7 at register address 0xAF).
The normal sequence of operation is;
1. Set the enable_quiet_I2C bit in TUNER_CTRL5.
2. Send/Receive the tuner I2C address and data as if it were being accessed directly by the host controller.
3. Reset the enable_quiet_I2C bit in TUNER_CTRL5.
Example: 0xD8
0xC0
0xAF
0xAA
0x80
0xBB...
; enable quiet I2C bus
; read/write any number of messages
; to tuner @ address 0xC0 for example
; disable quiet I2C bus
0xD8
0xAF
0x00
Reset
There are three types of reset. A hard reset is initiated at power up; cold and warm resets are initiated by
programming the RST_REG register (below). With cold and warm resets, the host controller determines the
type of reset and which parts of the CXD1968AR are to be reset.
Hard Reset
A hard reset is applied to all the CXD1968AR logic. A hard reset is initiated at power up by driving the
RESETN pin low for more than 28ns. When the CXD1968AR is powered up, it must be hard reset.
Whenever a hard reset occurs, the PLL will be out of tune. It must not drive logic until it has tuned. This
is prevented by the reset to any PLL clocked logic being held in reset after a hard reset. The host
controller must configure then enable the PLL output and release this reset after the PLL has tuned.
The PLL output is enabled by setting the PLL_op_enable bit in the PLL_CONTROL register. The reset
is released when the host controller resets the “hard” bit of the RST_REG register. The PLL tunes in
500μs.
Cold Reset
A cold reset is initiated by setting the cold bit in the RST_REG register, and resets any modules that
are selected by the RST_REG register, including their I2C registers.
Warm Reset
A warm reset is initiated by setting the warm bit in the RST_REG register, and resets any modules that
are selected by the RST_REG register, excluding their I2C registers.
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SONY [ SONY CORPORATION ]
