CXD1968AR
JTAG Test Interface
Test Mode
The JTAG interface consists of five test pins available on the CXD1968AR. These are used only for
embedded test and should be inactive for normal device operation. These pins are;
TRSTN Pin 34
TDO
TDI
TMS
TCK
Pin 30
Pin 31
Pin 32
Pin 29
The JTAG interface conforms to the “IEEE 1149.1 Joint Test Action Group (JTAG)” standard.
The following instructions are available:
Instruction
BYPASS
Code
1111
0000
0001
EXTEST
SAMPLE/PRELOAD
Normal Device Operation
The input functions of this group have very weak internal pull-ups present on the pins. This is primarily to
ensure that these pins cannot be left floating, a condition which could cause the device to draw excessive
current.
Under circumstances that may be influenced by board layout and supply power-up effects, the JTAG circuit
can be inadvertently activated in parallel with the normal operation of the demodulator. This results in the
main I2C bus locking.
This condition is readily identified but cannot be resolved without either a hardware reset or power-down.
Once the main I2C bus has locked it is not possible to communicate with the chip, hence only an external
reset will permit resumption of normal operation.
If JTAG functionality is not required, the interface should be disabled to ensure this mode cannot be
initiated. This is implemented by forcing the test block into permanent reset. The TRSTN and TCK inputs
should be grounded.
For users who wish to implement the JTAG test mode in their equipment, it will be unacceptable to
permanently ground the TRSTN and TCK inputs. It is suggested that these inputs are pulled to ground by
an external resistor. A pull-down value of 10kΩ is recommended, however the choice of value will depend
upon the driver circuit and speed of operation. This is illustrated in the application circuit in section 4.
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SONY [ SONY CORPORATION ]
