CXD1968AR
Forward Error Corrector Configuration
Operation of the FEC block can be optimized by overriding some of the default register values. The following
should be configured:
Viterbi auto-reset
Sync detect
TS output mode
Viterbi Block
The disable bit in the AUTO_RESET register should be reset to optimize acquisition (the default value does
not give optimum performance).
Example: 0xD8 0xB1 0x00
; enable Viterbi auto-reset
FEC Block
The SET_SYNC_DETECT register should be set to 0x67 for optimum performance (the default value of
0xD6 does not give optimum performance).
Example: 0xD8 0x86 0x67
; set sync detect
Transport Stream Outputs
Also, in order to obtain a watchable picture after TS lock, the transport stream outputs must be enabled
(normally these are tri-stated on power-up) by clearing bit 1 of FEC_PARAMS register. The following lines
enable the most commonly used parallel TS output format:
Example: 0xD8 0x80 0x18
0xD8 0x81 0xF4
; enable parallel mode
; preferred TS configuration
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