CXD1968AR
Tuner Control Interface
The Quiet I2C Module contained within the CXD1968AR allows the simple connection of slow I2C slave(s) to
a 400kHz master by providing the necessary logic to guarantee all of the timing parameters for the slower
device. If the slave is slower than 400kHz then it can use the slave acknowledge mechanism of holding the
clock low between high phases. The Quiet I2C Module does not provide for multi-master arbitration.
In order to satisfy the tuner's requirement that the bus is normally quiet, the slave interface may be enabled or
disabled.
PLL Operation
Internal clock signals are derived from an all-digital PLL. The functionality of this circuit has been extended to
allow operation with an optional external clock signal. A typical application could be to use a 4MHz clock
provided by the RF tuner, permitting the removal of the 20.48MHz crystal and components.
The following diagram illustrates the configuration used to generate the internal clock signals when a
20.48MHz crystal is present.
FIN
Range:
4 to 20MHz
& 20.48MHz
R[4:0]
OD[1:0]
FREF
Range:
2 to 8MHz
FOUT
Programmable
Reference Divider
Charge Pump
Loop Filter VCO
Programmable
Output Divider
φ
FVCO
Range:
200 to 400MHz
Programmable
Feedback Divider
Divide by 2
F[8:0]
In this example the clock source FIN is obtained from the crystal oscillator, running at a nominal 20.480MHz.
The reference divider R[4:0] is set to ÷5 which in combination with the fixed ÷2 results in FREF of 2.048MHz.
The feedback divider F[8:0] is set to ÷80 which in combination with the fixed ÷2 results in the VCO, FVCO
running at 327.68MHz (not accessible to the user).
The output frequency FOUT is divided by 4, OD[1:0] to give an 81.92MHz clock to the clock divider logic in
the demodulator core.
Refer to the registers PLL_FODR (0xA7) and PLL_F (0xA8) for detailed programming information and a table
of register settings for the supported external clock and crystal frequency combinations. The application note
EAN-0066 provides programming examples.
Note) The internal clock frequency of 20.48MHz can change to 20.50MHz for some clock configurations. This
will require alternative values of ITB_FREQ and TRL_NOM_RATE.
- 15 -
SONY [ SONY CORPORATION ]
