CXD1199AQ
2-1-19. DADRC-H register
This counter keeps the address for writing the data from the drive into the buffer. When drive data is written
into the buffer, the DADRC value is output from MA0 to 16. DADRC is incremented each time 1 byte of data
is written from the drive into the buffer.
The sub CPU sets the head address for buffer writing into DADRC before the decoder operates in the write-
only, real-time correction or CD-DA mode.
The sub CPU can set DADRC at any time. The contents of DADRC should not be changed while the
decoder is operating in any of the above modes.
2-1-20. HIFCTL (host interface control) register
bits 7 to 3 : Reserved
The sub CPU sets these bits low.
bit 2 : HINT#2
The value of this bit becomes that of HINTSTS#2 in the HINTSTS register on the host side.
bit 1 : HINT#1
The value of this bit becomes that of HINTSTS#1 in the HINTSTS register on the host side.
bit 0 : HINT#0
The value of this bit becomes that of HINTSTS#0 in the HINTSTS register on the host side.
2-1-21. RESULT register
This register is used to transfer the command execution result to the host. It has an 8-byte FIFO
configuration.
2-1-22. ADPMNT register
bit 7 : RTADPEN (real-time ADPCM enable)
The sub CPU sets this high to perform real-time ADPCM playback.
bits 6 to 0 : The upper 7 bits (bits 16 to 10) of the sector head address are written into these bits to perform
real-time ADPCM playback.
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SONY [ SONY CORPORATION ]
