CXD1199AQ
2-1-11. CLRINT (clear interrupt status) register
When each bit of this register is set high, the corresponding interrupt status is cleared. The bit concerned is
automatically set low after its interrupt status has been cleared. There is therefore no need for the sub CPU
to reset low.
bit 7 : DRVOVRN (drive overrun)
bit 6 : DECTOUT (decoder time out)
bit 5 : RSLTEMP (reset empty)
bit 4 : RTADPEND (real-time ADPCM end)
bit 3 : HDMACMP (host DMA complete)
bit 2 : DECINT (decoder interrupt)
bit 1 : HSTCMND (host command)
bit 0 : HCRISD (host chip reset issued)
2-1-12. HXFR-L (host transfer-low) register
2-1-13. HXFR-H (host transfer-high) register
bit 7 : DISHXFRC (disable host transfer counter)
High : The completion of the data transfer by HXFRC is disabled for data transfer between the host and
buffer memory.
Low : The completion of the data transfer by HXFRC is enabled for data transfer between the host and
buffer memory.
bits 6, 5 : Reserved
bit 4 : HADR16
HADR bit 16 (MSB)
bit 3 : HXFR11
HXFR (host transfer counter) bit 11 (MSB)
bit 2 : HXFR10
HXFR bit 10
bit 1 : HXFR9
HXFR bit 9
bit 0 : HXFR8
HXFR bit 8
The HXFR (host transfer) register sets the number of data transferred between the host and buffer memory.
The sub CPU sets this number when data is transferred between the host and buffer memory by setting the
DISHXFRC bit low.
2-1-14. HADR-L register
2-1-15. HADR-M register
2-1-16. HADR-H register
The HADR (host address) register is for the head addresses of data transfer between the host and buffer
memory.
2-1-17. DADRC-L register
2-1-18. DADRC-M register
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