CXD1199AQ
2-1-5. DLADR-L register
2-1-6. DLADR-M register
2-1-7. DLADR-H register
While the decoder is in the write-only, real-time correction or CD-DA mode, the last address is set for the
buffer write data from the drive. When the ENDLADR bit (bit 7) of the DECCTL register is high and the data
from the drive is written into the address assigned by DLADR while the decoder is in any of the above
modes, all subsequent writing in the buffer is prohibited.
2-1-8. CHPCTL (chip control) register
bit 7 : SM MUTE (sound map mute)
When this is set high, the audio output is muted for sound map ADPCM playback.
bit 6 : RT MUTE (real-time mute)
When this is set high, the audio output is muted for real-time ADPCM playback.
bit 5 : CD-DA MUTE
When bit 4 is high and this bit is also set high for CD-DA (digital audio) disc playback, the audio
output is muted. When bit 4 is low, this bit has no effect on the audio output.
bit 4 : CD-DA
High : Set high for playing back the audio signals of a CD-DA (digital audio) disc. Setting this bit high is
prohibited for ADPCM decoding playback.
Low : Set low for not playing back the audio signals of a CD-DA (digital audio) disc.
bit 3 : SWOPN (sync window open)
High : A window for sync mark detection is opened. In this case, the sync protection circuit in the IC is
disabled.
Low : The window for sync mark detection is controlled by the sync protection circuit in the IC.
bit 2 : RPSTART (repeat correction start)
Sector error correction starts when the decoder is set to the repeat correction mode, making this bit
high. This bit is automatically set low when correction starts. There is therefore no need for the
sub CPU to reset low.
bit 1 : DBLSPD (double speed)
Set high for double speed playback. Before changing the bit value, switch the CD DSP mode
(normal speed playback or double speed playback).
bit 0 : RESERVED
Normally set low.
2-1-9. INTMSK (interrupt mask) register
By setting each bit of this register high, the interrupt request from the IC to the sub CPU is enabled
depending on the corresponding interrupt status. (In other words, the INT pin is made active when its
interrupt status is established.) The each bit value of this register has no effect on the corresponding
interrupt status.
bit 7 : DRVOVRN (drive overrun)
The DRVOVRN status is established when the ENDLADR bit (bit 7) of the DECCTL register is set
high and DADRC and DLADR become equal while the decoder is in the write-only or real-time
correction mode. It is also established when they become equal while the decoder is in the CD-DA
mode regardless of the ENDLADR bit value.
bit 6 : DECTOUT (decoder time out)
The DECTOUT status is established when the sync mark is not detected even after 3 sectors (40.6
ms at normal speed playback) have elapsed after the decoder has been set to the monitor-only,
write-only or real-time correction mode.
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SONY [ SONY CORPORATION ]
