CXD1199AQ
2-2-7. INTSTS (interrupt status) register
The value of each bit in this register indicates that of the corresponding interrupt status. These bits are not
affected by the values of the INTMSK register bits.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
:
:
:
:
:
:
:
:
DRVOVRN (drive overrun)
DECTOUT (decoder time out)
RSLTEMPT (RESULT empty)
RTADPEND (real-time ADPCM end)
HDMACMP (host DMA complete)
DECINT (decoder interrupt)
HSTCMND (host command)
HCRISD (host chip reset issued)
2-2-8. ADPCI (ADPCM coding information) register
bit 7 : MUTE
This is high when the DA data is muted.
bit 6 : EMPHASIS
This is high when emphasis is applied to the ADPCM data.
bit 5 : ADPBUSY
This is high for ADPCM decoding.
bit 4 : BITLNGTH (bit length)
Indicates the bit length of the coding information for ADPCM playback.
High : 8 bits
Low : 4 bits
bit 2 : FS (sampling frequency)
Indicates the sampling frequency of ADPCM playback.
High : 18.9kHz
Low : 37.8kHz
bit 0 : S/M (stereo/mono)
Indicates the coding information stereo or mono for ADPCM playback.
High : Stereo
Low : Mono
2-2-9. HXFRC-L (host transfer counter-low) register
2-2-10. HXFRC-H (host transfer counter-high) register
The HXFRC counter indicates the number of remaining bytes in the data to be transferred between the host
and buffer memory. If sound map data is to be transferred before the data is transferred (immediately after
the host has set the BFRD and BFWR bits (bits 7 and 6) of the HCHPCTL register high), 2304 (900HEX) is
loaded into HXFRC. At any other time, the HXFR (sub CPU register) value is loaded. HXFRC is
decremented when data is read from the buffer memory (BFRD is high) or when the IC accepts data from the
host (BFWR is high).
2-2-11. HADRC-L (host address counter-low) register
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SONY [ SONY CORPORATION ]
