CXD1199AQ
bit 5 : RSLTEMPT (result empty)
The RSLTEMPT status is established when the host reads the result register and this register
becomes empty. (This is used when the number of result bytes sent to the host is 9 or more.)
bit 4 : RTADPEND (real-time ADPCM end)
The RTADPEND status is established when real-time ADPCM decoding is completed for one
sector.
bit 3 : HDMACMP (host DMA complete)
The HDMACMP status is established when DMA is completed by HXFRC.
bit 2 : DECINT (decoder interrupt)
The DECINT status is established when the sync mark is detected or inserted while the decoder is
in the write-only, monitor-only or real-time correction mode. However, it is not established if the
sync mark interval is less than 2352 bytes while the window for its detection is open. The status is
established each time one correction is completed when the decoder is in the repeat correction
mode.
bit 1 : HSTCMND (host command)
The HSTCMND status is established when the host writes a command in the command register.
bit 0 : HCRISD (host chip reset issued)
The HCRISD status is established when the host clears the IC. When HCRISD is high, the XHRS
pin is low.
2-1-10. CLRCTL (clear control) register
When each bit of the register is set high, the corresponding chip, status, register, interrupt status and
ADPCM playback are cleared. After clearing, the bit concerned is automatically set low. There is therefore
no need for the sub CPU to reset low.
bit 7 : CHPRST (chip reset)
The inside of the IC is initialized when this bit is set high. It is automatically set low upon
completion of the initialization.
bit 6 : CLRBUSY (clear busy)
The BUSYSTS bit of the HIFSTS register is cleared when this bit is set high.
bit 5 : CLRRSLT (clear result)
The RESULT register is cleared when this bit is set high.
bit 4 : RTADPCLR (real-time ADPCM clear)
(1) When this is set high for real-time ADPCM playback (when the RTADPBSY bit of the DECSTS
register is high):
• ADPCM decoding during playback is suspended. (Noise may be generated.)
• The RTADPEND interrupt status is established.
(Note) The RTADPEN bit (bit 7 of the ADPMNT register) must be set low before this bit is set
high.
(2) Setting this bit high when real-time ADPCM playback is not being performed has no effect
whatsoever.
bits 3 to 1 : Reserved
Normally set low.
bit 0 : RESYNC
The CD DSP and this IC are synchronized when this bit is set high. Set the bit high by the sub
CPU in the following cases:
(1) After the DRVIF register has been set
(2) After the DBLSPD bit (bit 1 of the CHPCTL register) has been set low.
This bit is automatically set low when the CD DSP and this IC are synchronized.
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SONY [ SONY CORPORATION ]
