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CXD1199AQ 参数 Datasheet PDF下载

CXD1199AQ图片预览
型号: CXD1199AQ
PDF下载: 下载PDF文件 查看货源
内容描述: 的CD-ROM解码器 [CD-ROM DECODER]
分类和应用: 解码器消费电路商用集成电路
文件页数/大小: 42 页 / 348 K
品牌: SONY [ SONY CORPORATION ]
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CXD1199AQ  
bit 2 : DAMIXEN (digital audio mixer enable)  
High : Attenuator and mixer are not activated for CD-DA.  
Low : Attenuator and mixer are activated for CD-DA.  
bit 1 : DACODIS (DAC out disable)  
High : Clock signals are output from the WCKO, LRCO and BCKO pins even for muting.  
Low : The WCKO, LRCO and BCKO pins are set low for muting.  
bit 0 : Reserved  
Normally fixed low.  
2-1-4. DECCTL (decoder control) register  
bit 7 : ENDLADR (enable drive last address)  
High : DLADR (drive last address) is enabled when this is high. When DADRC and DLADR become  
equal while the decoder is in the write-only, real-time correction or CD-DA mode, the data writing  
from the driver into the buffer is stopped.  
Low : DLADR (drive last address) is disabled when this is low. Even when DADRC and DLADR become  
equal while the decoder is in the write-only, real-time correction or CD-DA mode, data writing from  
the driver into the buffer is not stopped.  
bit 6 : ECCSTR (ECC strategy)  
High : Errors are corrected with consideration given to the error flags of the data.  
Low : Errors are corrected with no consideration given to the error flags of the data. In this case, there is  
no erasure correction. Set this bit low when the IC is connected to an 8-bit/word SRAM.  
bit 5 : MODESEL (mode select)  
bit 4 : FORMSEL (form select)  
When AUTODIST is low, the sector is corrected in the MODE or FORM indicated below.  
MODESEL  
FORMSEL  
“L”  
“H”  
“H”  
“L”  
“L”  
“H”  
MODE1  
MODE2, FORM1  
MODE2, FORM2  
bit3  
: AUTODIST (auto distinction)  
High : Errors are corrected according to the MODE byte and FORM bit read from the drive.  
Low : Errors are corrected according to the MODESEL and FORMSEL bits (bits 5 and 4).  
bits 2 to 0 : DECMD2 to 0 (decoder mode 2 to 0)  
DECMD2  
“L”  
DECMD1  
“L”  
DECMD0  
“X”  
Decoder disable  
“L”  
“H”  
“X”  
Monitor-only mode  
Write-only mode  
“H”  
“L”  
“L”  
“H”  
“L”  
“H”  
Real-time correction mode  
Repeat correction mode  
CD-DA mode  
“H”  
“H”  
“L”  
“H”  
“H”  
“H”  
When the CD-DA bit (bit 4) in the CHPCTL register is to be set high, set the decoder to the disable  
or CD-DA mode.  
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