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CXD1199AQ 参数 Datasheet PDF下载

CXD1199AQ图片预览
型号: CXD1199AQ
PDF下载: 下载PDF文件 查看货源
内容描述: 的CD-ROM解码器 [CD-ROM DECODER]
分类和应用: 解码器消费电路商用集成电路
文件页数/大小: 42 页 / 348 K
品牌: SONY [ SONY CORPORATION ]
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CXD1199AQ  
2-1-1. CONFIG1 (configuration 1) register  
This register is set depending on the IC peripheral hardware. The sub CPU sets this register after the IC has  
been reset.  
bit 7 : Reserved  
Normally set low.  
bit 6 : XSLOW  
The number of clock signals per DMA cycle is determined by this bit.  
High : 4 clock signals  
Low : 12 clock signals  
Set low when a low-speed SRAM is connected for VDD = 3.5 V. When XSLOW is low, erasure  
correction and double speed playback are prohibited.  
bit 5 : PRTYCTL (priority control)  
Set high when double speed playback with erasure correction executed is performed by setting the  
clock frequency of the CD-ROM decoder to 18 MHz or below. In this case, buffer access for ECC  
has priority and the rate of data transfer to the host is reduced.  
When a 9-bit/word SRAM has been connected to this IC, the C2 pointer is written from the BDBP  
pin into the buffer memory regardless of this bit value.  
bits 4, 3 : RAMSZ1, 0 (RAM size 1, 0)  
bit 2 : 9 BITRAM  
These bits are set depending on the size of the SRAM connected to the IC.  
RAMSZ1  
“L”  
RAMSZ0  
“L”  
9 BITRAM  
SRAM size  
32 Kw × 8b  
32 Kw × 9b  
64 Kw × 8b  
64 Kw × 9b  
128 Kw × 8b  
128 Kw × 9b  
“L”  
“H”  
“L”  
“H”  
“L”  
“H”  
“L”  
“L”  
“L”  
“H”  
“L”  
“H”  
“H”  
“L”  
“H”  
“L”  
bit 1 : CLKDIS (CLK disable)  
High : The CLK pin is fixed low.  
Low : A 16.9344 MHz clock signal is output from the CLK pin.  
bit 0 : HCLKDIS (half CLK disable)  
High : The HCLK pin is fixed low.  
Low : An 8.4672 MHz clock signal is output from the HCLK pin.  
2-1-3. CONFIG2 (configuration 2) register  
This register is set depending on the IC peripheral hardware. The sub CPU sets this register after the IC has  
been reset.  
bits 7, 6 : Reserved  
Normally set low.  
bit 5 : SPECTL (sound parameter error control)  
bit 4 : SPMCTL (sound parameter majority control)  
These two bits control the processing of the sound parameters for ADPCM decoding playback.  
bit 3 : SMBF2 (sound map buffer 2)  
Indicates the number of buffer surfaces for the sound map ADPCM.  
High : 2 buffer surfaces for the sound map  
Low : 3 buffer surfaces for the sound map  
—22—  
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