CXD1199AQ
2. Sub CPU Registers
2-1. Write registers
2-1-1. DRVIF (drive interface) register
This register controls the connection mode with the CD DSP. After the IC has been reset, the sub CPU sets
this register according to the CD DSP to be connected.
bit 7 : C2PL1ST (C2PO lower byte 1st)
High : When two bytes of data are input, C2PO inputs the lower byte first followed by the upper byte.
Low : When two bytes of data are input, C2PO inputs the upper byte first followed by the lower byte.
Here, “upper byte” means the upper 8 bits including MSB from the CD DSP and “lower byte”
means the lower 8 bits including LSB from the CD DSP. For instance, the header minute byte is
the lower byte and the second byte, the upper byte.
bit 6 : LCHLOW (Lch low)
High : When LRCK is low, determined to be the left channel data.
Low : When LRCK is high, determined to be the left channel data.
bit 5 : BCKRED (rising edge of BCLK)
High : The DATA is strobed at the rising edge of BCLK.
Low : The DATA is strobed at the falling edge of BCLK.
bits 4, 3 : BCKMD1, 0 (BCLK mode 1, 0)
These bits are set according to the number of clocks output for BCLK during one WCLK cycle by
the CD digital signal processor LSI (CD DSP).
BCKMD1
“L”
BCKMD0
“L”
16 BCLKs/WCLK
24 BCLKs/WCLK
32 BCLKs/WCLK
“L”
“H”
“H”
“X”
bit 2 : LSB1ST (LSB first)
High : Connected with the CD DSP which outputs DATA with LSB first.
Low : Connected with the CD DSP which outputs DATA with MSB first.
bits 1, 0 : Reserved
Normally set below.
Any change of each bit value in this register must be made in the decoder disable status.
Table 2-1-1 shows the settings for bits 7 to 2 when this IC is connected to Sony’s CD DSP.
Figs. 2-1-1 (1) to (3) are input timing charts.
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SONY [ SONY CORPORATION ]
