CXD1199AQ
1-6. Others (16 pins)
(1) MUTE (mute : output)
Outputs high when the DA data (DATO) is muted.
(2) XRST (reset : input)
Chip reset negative logic input signal.
(3) XTL1 (crystal1 : input)
(4) XTL2 (crystal2 : output)
A 16.9344 MHz crystal oscillator is connected between XTL1 and XTL2. (The capacitor value depends
on the crystal oscillator.)
Alternatively, a 16.9344 MHz clock signal is input to the XTL1 pin.
(5) CLK (clock : output)
Outputs a 16.9344 MHz clock signal. The output can be fixed low when this signal is not used.
(6) HCLK (half clock : output)
Outputs an 8.4672 MHz clock signal. The output can be fixed low when this signal is not used.
(7) CKSL (clock select : input)
High or open : The IC is operated by the XTL1 clock.
Low : The audio block (ADPCM decoder and digital filter) is operated by the XTL1 clock, and the CD-
ROM decoder unit is operated by the RMCK clock. In this case, the slow mode described later is
prohibited.
This pin is pulled up by a 50 kΩ standard resistor in the IC.
(8) RMCK (ROM clock : input)
When the CKSL pin is set low, the clock of the CD-ROM decoder unit is input. When it is high or open,
fix the RMCK pin high or low.
(9) XHRS (host reset : output)
This pin is low when the IC has been reset by the host. It is an open drain output.
(10) TD0 to 7 (test data 0 to 7 : input/output)
The data pins for testing the IC. They are pulled up by a 25 kΩ standard resistor and are normally left
open.
1-7. Power supply pins (12 pins)
VDD : 4 pins ; GND: 8 pins
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SONY [ SONY CORPORATION ]
