CXD1185CQ/CR
5-1. Program I/O transfer
This method is used to transfer data between the CPU bus and the CXD1185C. The CPU manages SCSI
handshaking entirely through software. By issuing the “Assert SCSI Control” and “Assert SCSI Data”
commands, all of the SCSI bus bits can be software controlled. After the above two commands are issued,
values can be written to the SCSI bus control register and the SCSI data register to carry out the SCSI
handshake.
When the “Assert SCSI Data” command is issued, the CXD1185C internal FIFO counter is fixed at “0”. As a
result, only one byte of data can be received by the data register. Reading the SCSI data register results in
reading the SCSI data bus directly. If the CXD1185C is in neither initiator nor target mode (status register
bits 4 and 3 both set to “0”), none of the bits in the SCSI bus control register can be output to the SCSI bus
except ABSY and ASEL. If the CXD1185C is in initiator mode, the AACK and AATN bits are output to the
SCSI bus. In the target mode, the AMSG, ACD, AIO and AREQ bits are output.
When phase change (PHC) interrupt occur in initiator mode, output to the SCSI data bus is inhibited. In such
case, read the SCSI control monitor register and set the phase in the SCSI control register. When “Assert
SCSI Control” command is executed in target mode, pins on the SCSI bus, except BSY, are released.
The phase can be controlled by setting appropriate values to the SCSI bus control register. The contents of
the SCSI control register and/or SCSI data register are output continually after “Assert SCSI Control” and/or
“Assert SCSI data”. Therefore, when program I/O transfer is completed the “Deassert SCSI Control” or
“Deassert SCSI Data” command must be written to the command register.
5-2. CPU I/O transfer
This method is used to transfer data between the CPU bus and the CXD1185C without using DMA. Transfer
command can be issued when the CPU is in either the initiator or the target mode. When issuing these
commands, command register bit 5 (DMA) must be set to “0”.
• Outputting data to the SCSI bus
During the transfer, the CPU must monitor the FIFO status and make sure that it does not attempt to write
to the FIFO when it is full (FIFO is full when FIF bit in the FIFO status register is “1”) ( ). In target mode,
after issuing the transfer command, the CPU must check that the SCSI bus phase is changed to the
appropriate phase, by software, before any transfer data is written.
( ) Before writing a value to the data register a transfer command must be written to the command register.
• Reading data from the SCSI bus
After a transfer command is written to the command register, the CPU must monitor the FIE bit in the FIFO
status register so as to make sure that it does not attempt to read an empty FIFO. The CPU must monitor
the FNC bit in the status register to detect the end of transfer. The CPU, at the end of the transfer, must
continue to read any remaining data in the FIFO.
5-3. DMA transfer
This method is used to transfer data between the DMA bus and the CXD1185C. Transfer commands can be
issued when the CPU is in either the initiator or the target mode. When issuing commands command
register bit 5 (DMA) and 4 (TRBE) must be set to “1”. When a transfer is initiated the DRQ pin becomes
active. Then, when the DACK pin becomes active, the DRQ pin becomes inactive (when mode register bit 0
(BDMA) is set to “0”) and one byte of data is either written to or read from the FIFO. If the environment
setting register bit 5 (DPEN) is set to “1”, the data bus parity is calculated from the DP pin. During reads the
parity bit is generated, and during writes parity bit check takes place. During DMA transfer, the CPU bus and
data register are cut off. Hence, data register reads/writes from the CPU are ignored.
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SONY [ SONY CORPORATION ]
