CXD1185CQ/CR
4-2. Interrupts when selected/reselected
After “Enable Selection/Reselection” is executed, if the owner ID and the SEL signal appear on the SCSI bus,
SWOA bit is set to “1”. If ATN signal also appear at the same time, SWA bit is set instead. If I/O signal
appears instead of ATN signal, then, RSL is set. When any interuppt is generated, the FNC bit is set to “1”
after a while (6 µs max.). The next command cannot be written in the command register till the bit is set.
4-3. Interrupts when selection/reselection command is executing
When any of “Reselect”, “Select without ATN” or “Select with ATN” command is executed, the CXD1185C
enters arbitration and after obtaining the right to use the SCSI bus it enters selection/reselection phased by
sending the target ID, the owner ID and SEL signal onto the bus. At this point, the value of the
selection/reset timer register is loaded into the hardware timer (not user accessible) and decrementing
begins. Note that TMSL bit in the mode register must be “1” for the loading to take place. If there is no
response from the target device by the time the hardware timer reaches “0”, selection time over occurs and
the STO bit is set to “1” and, afterward, the FNC bit is set to “1”.
4-4. Data transfer phase interrupts
• The RMSG and PHC bits are valid interrupts only when INIT bit (status register bit 4) is set to “1”. Also, the
DATN bit is valid only when the TARG bit (status register bit 3) is set to “1”. The SPE and DPE bits are
valid both in initiator and target modes.
• The RMSG bit is set to “1”, if, in initiator mode, the target device activates REQ after changing the SCSI
bus phase to either Message-In or Message-Out. If the message is of multiple byte, it is set each time
REQ in activated.
• The PHC bit is set to “1”, if, in initiator mode, the target device activates REQ after changing the SCSI bus
phase. If the new phase is either Message-In or Message-Out, RMSG bit is also set to “1”.
• The DATN bit is set to “1”, if, in target mode, the initiator asserts ATN on the SCSI bus. Once the interrupt
request register 2 is read by the CPU, the bit is cleared even if ATN continues to be active.
• The SPE bit is set when a parity error is detected on the SCSI bus during receive mode data transfer in
both initiator and target mode. In initiator mode, it is set on receiving the REQ. In target mode it is set on
receiving the ACK. The SPE bit is also set if parity error is detected during selection/reselection.
• DPE bit is set when a parity error is detected on the data bus while writing data into FIFO. It is set at the
rise of the FIFO write signal, WED. This bit is valid only if the DPEN bit in the environment setting register
is set to “1”. If the SDPM bit in the environment register is “1”, even parity check is carried out. Otherwise
odd parity check is carried out.
4-5. Other interrupt
• The SRST bit is set to “1” when the SCSI bus RST signal becomes active. It is also set if the “Assert RST”
command is executed and the CXD1185C drives the RST pin.
• The DCNT bit is set to “1” if the CXD1185C is operating in the initiator mode and the target device makes
the BSY signal on the SCSI bus inactive. Normally, in initiator mode, this bit is set at the end of a series of
SCSI operation when the SCSI bus phase becomes bus free.
5. Data Transfer
In this section procedures for transferring data to and from the CXD1185C is described. Data can be
transferred between the CPU and the CXD1185C in the following three ways :
1. Program I/O transfer
2. CPU I/O transfer
3. DMA transfer
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SONY [ SONY CORPORATION ]
