CXD1185CQ/CR
3. Reset Operation
There are four initializing methods for the CXD1185C :
• hardware reset
• execution of the “Reset Chip” command
• assertion of RST signal on the SCSI bus
• disconnect
3-1. Hardware reset
This returns the CXD1185C to its initial status.
However, environment setting register bit 1 (FS1) is set to “1”, making the initial clock division ratio to “4”. All
of the internal circuits are also initialized.
At this time, the selection/reselection interrupt are disabled.
3-2. Execution of the “Reset Chip” command
The CXD1185C can be initialized by “Reset Chip” command (command code “01”). This command is
effective regardless of the CIP bit in the status register.
This command resets all registers with the exception of the environment setting register.
All read only registers except for bits 7 and 6 of the status register and the SCSI control monitor register are
cleared.
Since the “Reset Chip” command clears all write registers, any SCSI bus signal being driven by the
CXD1185C will also be cleared.
At this time, the selection/reselection interrupt are disabled.
3-3. Assertion of RST signal on the SCSI bus
When the SCSI bus RST signal is active, signals on the SCSI bus being driven by the CXD1185C are made
inactive with the exception of the RST pin.
Bits 4 and 3 (INIT and TARG bits) are also cleared.
3-4. Disconnect
If the CXD1185C is operating in initiator mode and a disconnect interrupt is generated, a reset identical to the
one in 3-3 takes place.
4. Interrupt Operation
In this section various interrupts, generated by the CXD1185C, are discussed in greater detail. If the
internal interrupt conditions of the CXD1185C are satisfied, “1”s are written to the appropriate bits in
interrupt request registers 1 and 2 and the MIRQ bit in the status register. IRQ pin becomes active only if
the interrupt is authorized in the interrupt authorization registers.
4-1. Arbitration interrupt
When a selection command is executed, the CXD1185C waits for bus free. Once bus free is detected it
outputs the BSY signal and the owner ID to the SCSI bus and enters arbitration. If, during arbitration,
another device with higher priority enters arbitration or if the SEL signal is driven on the SCSI bus, arbitration
fails and ARBF is set to “1”. The FNC bit is also set a while later. However, if it is not in the bus free state
when the selection command is executed, the above operation is performed after bus free is detected. If
arbitration is successful it enters selection phase.
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SONY [ SONY CORPORATION ]
