CXD1185CQ/CR
• Enable Selection/Reselection
Activates selection/reselection interrupts.
When this command is executed, the FNC bit is set immediately and the contents of the CIP bit and
command register are cleared. Once this command is executed, RSL/SWA/SWOA interrupts (in interrupt
request 1 register) are set during selection/reselection phase. When one of the selection/reselection is
executed this will occur before the FNC interrupt.
Selection/reselection is automatically disabled for the cases below.
· Hardware reset
· Execution of “Reset Chip”
If one of the above conditions occurs, an “Enable Selection/Reselection” command must be reloaded in the
command register in order to accommodate selection/reselection interrupt.
• Disable Selection/Reselection
Prohibits any response to selection/reselection.
Once this command is executed, the RSL/SWOA/SWA interrupts in interrupt request register 1 will not be
generated.
2-3. Commands valid in target status
The following commands are valid only in target status.
If any of these commands are issued in any other state, the CIP bit and the content of the command register
are cleared immediately.
In the case of data send commands, the transfer data must not be written before the command is written in
the command register and the necessary SCSI phase change is confirmed by software. In target mode,
handshaking on the SCSI bus is terminated under the following conditions :
1. The REQ signal is in any state and if :
· a hardware reset is performed.
· the “Reset Chip” command is executed.
· the SCSI bus RST pin is driven.
2. The command completes with REQ inactive if :
· a parity error is generated on the SCSI bus or the data bus.
(However, this is not the case if the mode register HDPE and HSPE bits are set to “0”.)
· the SCSI bus ATN signal is driven.
(However, this is not the case if the mode register HATN bit is set to “0”.)
· while the transfer byte counter is in use :
the DMA bit is set to “1”, the status register TRBZ bit is set to “1” and the FIFO status register FIE bit is
set to 1, or in receive mode, the DMA bit is set to “0” and the status register TRBZ bit is set to “1”.
· while executing a single byte transfer :
the mode is send and the FIE bit is set to “1”,
or the mode is receive and FIFO status register bits FC3-FC0 are all set to “1”.
3. Handshaking is temporarily interrupted with REQ inactive if :
· while the transfer byte counter is in use :
the mode is send and the FIFO status register FIE bit is set to “1”,
or the mode is receive and the FIFO status register FIF bit is set to “1”.
· during synchronous transfer, the difference in the number of REQ and ACK reaches the offset specified
in the synchronous transfer register.
· the mode is receive, during synchronous transfer, the number of FIFO bytes remaining is fewer than the
offset specified in the synchronous transfer register.
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