Table 16 – GPIO Interrupt Mask Register
GPIO_MSK
(0x9C- RESET=0xFF)
GPIO INTERRUPT MASK REGISTER
DESCRIPTION
BIT
NAME
R/W
7
GPIO7_MSK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051.
6
5
4
3
2
1
0
GPIO6_MSK
GPIO5_MSK
GPIO4_MSK
GPIO3_MSK
GPIO2_MSK
GPIO1_MSK
GPIO0_MSK
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051..
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051...
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051...
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051...
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051...
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051...
1 = Prevents a high in the corresponding bit
in the GPIO_IRQ register from generating an
interrupt on the INT4 input to the 8051...
SMSC DS – USB97C201
Page 25
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
