Table 13 - GPIO Output Register
GPIO_OUT
GPIO DATA OUTPUT
REGISTER
(0x9A- RESET=0x00)
BIT
7
NAME
GPIO7
R/W
DESCRIPTION
GPIO7 Output Buffer Data
GPIO6 Output Buffer Data
GPIO5 Output Buffer Data
GPIO4 Output Buffer Data
GPIO3 Output Buffer Data
GPIO2 Output Buffer Data
GPIO1 Output Buffer Data
GPIO0 Output Buffer Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
GPIO6
5
GPIO5
4
GPIO4/nWE
GPIO3/T1
GPIO2/T0
GPIO1/TXD
GPIO0/RXD
3
2
1
0
Table 14 - GPIO Input Register
GPIO_IN
(0x9B- RESET=0x00)
GPIO INPUT REGISTER
DESCRIPTION
BIT
NAME
GPIO7
R/W
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
GPIO7 Input Buffer Data
GPIO6 Input Buffer Data
GPIO5 Input Buffer Data
GPIO4 Input Buffer Data
GPIO3 Input Buffer Data
GPIO2 Input Buffer Data
GPIO1 Input Buffer Data
GPIO0 Input Buffer Data
GPIO6
GPIO5
GPIO4/nWE
GPIO3/T1
GPIO2/T0
GPIO1/TXD
GPIO0/RXD
Table 15 – GPIO Interrupt Status Register (INT4)
GPIO_IRQ
(0XC0- RESET=0x00)
GPIO INTERRUPT STATUS REGISTER
DESCRIPTION
BIT
7
NAME
R/W
GPIO7_IRQ
GPIO6_IRQ
GPIO5_IRQ
GPIO4_IRQ
GPIO3_IRQ
GPIO2_IRQ
GPIO1_IRQ
GPIO0_IRQ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = A level change has occurred on GPIO7.
1 = A level change has occurred on GPIO6.
1 = A level change has occurred on GPIO5.
1 = A level change has occurred on GPIO4.
1 = A level change has occurred on GPIO3.
1 = A level change has occurred on GPIO2.
1 = A level change has occurred on GPIO1.
1 = A level change has occurred on GPIO0.
6
5
4
3
2
1
0
Note 1: Writing a “1” (one) to a bit clears the bit and enables the detection of the next level transition. If not masked
by the corresponding bit in the GPIO_MSK register, “1” in any bit in this register will force a “1” on the 8051
core’s external INT4 interrupt input.
SMSC DS – USB97C201
Page 24
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
