Table 9 - Interrupt 1 Mask
INTERRUPT 1 MASK REGISTER
IMR_1
(0x94- RESET=0xFF)
BIT
NAME
R/W
DESCRIPTION
Zero Length Packet Interrupt Mask
0 = Enable Interrupt
7
ZLP_EP0
R/W
1 = Mask Interrupt
6
5
Resereved
ATA_PIO
R/W
R/W
Reserved. This bit should never be written to a “0”.
ATA PIO Complete Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
4
3
2
1
0
EP1RX
EP1TX
R/W
R/W
R/W
R/W
R/W
Endpoint 1 Received Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 1 Transmitted Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
EP0RX
Endpoint 0 Received Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
EP0TX
Endpoint 0 Transmitted Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SUSPEND
SUSPEND Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Note 1: The mask bits do not prevent the status in the ISR_1 register from being set, only from generating an
interrupt.
Table 10 - Device Revision Register
DEV_REV
(0x95- RESET=0xXX)
R/W
DEVICE REVISION REGISTER
DESCRIPTION
BIT
[7:0]
XXh
R
This register defines additional revision information
used internally by SMSC. The value is silicon revision
dependent.
Table 11 - Device Identification Register
DEV_ID
(0x96- RESET=0x12)
R/W
DEVICE IDENTIFICATION REGISTER
DESCRIPTION
BIT
[7:0]
12h
R
This register defines additional revision information
used internally by SMSC
SMSC DS – USB97C201
Page 21
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
