SIE & BUFFER CONTROL REGISTERS
A9
AA
AB
AC
B0
AD
AE
AF
B1
B2
B3
B4
B5
B6
B7
C7
CE
CF
D1
D2
D3
D4
D5
D6
D7
D9
DA
USB_ADD
SIE_CONF
R/W
R/W
R/W
R/W
R
USB Address Register
29
29
30
30
31
32
31
32
32
32
33
33
34
35
35
35
35
35
35
36
36
36
36
36
36
37
39
SIE Configuration Register
USB_STAT
USB_MSK
USB Bus Status Register
USB Bus Status Mask Register
SIE Status Register
SIE_STAT
USB_CONF
SIE_MSK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
USB Configuration Number Register
SIE Status Mask Register
EP0RX_CTL
EP0TX_CTL
EP1RX_CTL
EP1TX_CTL
EP2_CTL
Endpoint 0 Receive Control Register
Endpoint 0 Transmit Control Register
Endpoint 1 Receive Control Register
Endpoint 1 Transmit Control Register
Endpoint 2 Control Register
EP0RX_BC
EP0TX_BC
EP1RX_BC
EP1TX_BC
RAMWRBC_A1
RAMWRBC_A2
RAMWRBC_B1
RAMWRBC_B2
RAMRDBC_A1
RAMRDBC_A2
RAMRDBC_B1
RAMRDBC_B2
NAK
Endpoint 0 Receive Byte Count Register
Endpoint 0 Transmit Byte Count Register
Endpoint 1 Receive Byte Count Register
Endpoint 1 Transmit Byte Count Register
RAM Buffer Write Byte Count Register A1
RAM Buffer Write Byte Count Register A2
RAM Buffer Write Byte Count Register B1
RAM Buffer Write Byte Count Register B2
RAM Buffer Read Byte Count Register A1
RAM Buffer Read Byte Count Register A2
RAM Buffer Read Byte Count Register B1
RAM Buffer Read Byte Count Register B2
NAK Status Register
NAK_MSK
NAK Mask Register
USB_ERR
USB Error Register
ATA CONFIGURATION REGISTERS
DB
DC
DD
DE
DF
E1
E2
E3
E4
E5
E6
MSB_ATA
LSB_ATA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSB ATA Data Register
38
38
39
40
40
38
38
38
39
42
42
LSB ATA Data Register
ATA_CTL
ATA Control Register
ATA_DMA
IDE_TIM
ATA Ultra DMA Timing Register
IDE Timing Register
ATA_CNT0
ATA_CNT1
ATA_CNT2
ATA_CNT3
ATA_SRCA
ATA_SRCB
ATA Transfer Count Register 0
ATA Transfer Count Register 1
ATA Transfer Count Register 2
ATA Transfer Count Register 3
ATA Slew Rate Control A Register
ATA Slew Rate Control B Register
SMSC DS – USB97C201
Page 17
Rev. 03/25/2002
PRELIMINARY