9
AC PARAMETERS
t1
t2
t2
CLOCKI
FIGURE 1 - INPUT CLOCK TIMING
Table 2 – Input Clock Timing Parameters
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
ns
t1
t2
Clock Cycle Time for 14.318MHz
69.84
Clock High Time/Low Time for 24MHz
41.9/
27.9
27.9/
41.9
ns
tr, tf
Clock Rise Time/Fall Time (not shown)
5
ns
t1
t5
FA[0:19
t3
t4
FD[7:0
nFRD
t2
nFWR
FIGURE 2 – FLASH READ TIMING
Table 3 – Flash Read Timing
NAME
PARAMETER
FA[14:0] Address setup time to nFRD asserted
MIN
TYP
MAX
UNITS
ns
t1
t2
t3
t4
t5
40
110
30
0
nFRD pulse width
ns
FD[7:0] Data setup time to nFRD de-asserted
FD[7:0] Data hold time from nFRD de-asserted
FA[14:0] Address hold time from nFRD de-asserted
ns
ns
35
ns
SMSC DS – USB97CFDC2-01
Page 17
Rev. 02-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
