Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
4.2
Clock Specifications
Table 4.2 ULPI Clock Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Suspend Recovery Time
Note 4.3
TSTART
26MHz REFCLK
12MHz REFCLK
52MHz REFCLK
24MHz REFCLK
19.2MHz REFCLK
27MHz REFCLK
38.4MHz REFCLK
13MHz REFCLK
1.03
2.24
0.52
1.12
1.40
1.00
0.70
2.07
0.45
2.28
3.49
1.77
2.37
2.65
2.25
1.95
3.32
0.5
ms
ms
ms
ms
ms
ms
ms
ms
ms
PHY Preparation Time
TPREP
60MHz REFCLK
ULPI Input Clock Mode
0.4
CLKOUT Duty Cycle
REFCLK Duty Cycle
DCCLKOUT ULPI Input Clock Mode
45
20
55
80
%
DCREFCLK
%
REFCLK Frequency Accuracy FREFCLK
-500
+500
PPM
Note 4.3 The Suspend Recovery Time is measured from the start of the REFCLK to when the
USB3320 de-asserts DIR.
Note: The USB3320 uses the AutoResume feature, Section 6.2.4.4, to allow a host start-up time of
less than 1ms
4.3
ULPI Interface Timing
Table 4.3 ULPI Interface Timing
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
60MHz ULPI Output Clock Note 4.4
Setup time (STP, data in)
T
SC, TSD
Model-specific REFCLK
5.0
0.0
1.0
ns
ns
ns
Hold time (STP, data in)
THC, THD Model-specific REFCLK
Output delay (control out, 8-bit data out)
60MHz ULPI Input Clock
TDC, TDD Model-specific REFCLK
3.5
6.0
Setup time (STP, data in)
T
SC, TSD
THC, THD 60MHz REFCLK
TDC, TDD 60Mhz REFCLK
60MHz REFCLK
1.5
-0.5
1.5
ns
ns
ns
Hold time (STP, data in)
Output delay (control out, 8-bit data out)
Note: VDD18 = 1.6 to 2.0V; VSS = 0V; TA = -40°C to +85°C
Note 4.4 REFCLK does not need to be aligned in any way to the ULPI signals.
Revision 1.0 (07-14-09)
SMSC USB3320
DATA1S6HEET
SMSC [ SMSC CORPORATION ]
