Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PCI_CLK
nLFRAME
L1 L2
Address
TAR
Sync=0110
L3
Data
TAR
LAD[3:0]
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
Figure 13.8 - I/O Read
PCI_CLK
nLDRQ
Start
MSB
LSB
ACT
Figure 13.9 – DMA Request Assertion Through NLDRQ
PCI_CLK
LFRAME#
LAD[3:0]
Start C+D CHL Size
TAR
Sync=0101
L1
Data
TAR
Note: L1=Sync of 0000
Figure 13.10 – DMA Write (First Byte)
PCI_CLK
nLFRAME
LAD[3:0]
Start C+D CHL Size
Data
TAR
Sync=0101
L1
TAR
Note: L1=Sync of 0000
Figure 13.11 – DMA Read (First Byte)
SMSC LPC47M182
203
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET