Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
t1
CLOCKI
t2
t2
Figure 13.2 - Input Clock Timing
DESCRIPTION
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
NAME
MIN
TYP
69.84
35
31.25
15.63
MAX
UNITS
ns
ns
µs
µs
t1
t2
t1
t2
20
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
5
ns
t1
t4
t2
t5
t3
P C I_C LK
Figure 13.3 - PCI Clock Timing
DESCRIPTION
NAME
MIN
30
12
TYP
MAX
33.3
UNITS
nsec
nsec
nsec
nsec
nsec
t1
t2
t3
t4
t5
Period
High Time
Low Time
Rise Time
Fall Time
12
3
3
t1
nPCI_RESET
Figure 13.4 - Reset Timing
NAME
t1
DESCRIPTION
MIN
1
TYP MAX
UNITS
ms
nPCI_RESET width
SMSC LPC47M182
201
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
