Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
t1
t3
t2
nWRITE
PD<7:0>
t4
t5
t6
t7
t8
t9
t10
nDATASTB
nADDRSTB
t11
t12
nWAIT
Figure 13.14 – EPP 1.9 Data Or Address Read Cycle
NAME
DESCRIPTION
MIN
0
60
60
0
0
60
0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
nWAIT Asserted to nWRITE Deasserted
nWAIT Asserted to nWRITE Modified (Notes 1,2)
nWAIT Asserted to PDATA Hi-Z (Note 1)
Command Asserted to PDATA Valid
Command Deasserted to PDATA Hi-Z
nWAIT Asserted to PDATA Driven (Note 1)
PDATA Hi-Z to Command Asserted
nWRITE Deasserted to Command
nWAIT Asserted to Command Asserted
nWAIT Deasserted to Command Deasserted
(Note 1)
185
190
180
190
30
1
0
60
195
180
ns
ns
t11
t12
PDATA Valid to nWAIT Deasserted
PDATA Hi-Z to nWAIT Asserted
0
0
ns
µs
Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.
Note 2: When not executing a write cycle, EPP nWRITE is inactive high.
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
206
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
