Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 13 Timing Diagrams
For the Timing Diagrams shown, the following capacitive loads are used on outputs.
CAPACITANCE
TOTAL (pF)
NAME
SER_IRQ
LAD [3:0]
50
50
nLDRQ
nDIR
nSTEP
nDS0
PD[0:7]
nSTROBE
nALF
KDAT
KCLK
50
240
240
240
240
240
240
240
240
240
240
50
MDAT
MCLK
TXD
YLW_LED
GRN_LED
nIDE_RSTDRV
nPCIRST_OUT
nPCIRST_OUT2
PS_ON
50
50
40
40
40
50
SCK_BJT_GATE
PWRGD_PLATFORM
nCDC_DWN_ENAB/
GP24
50
50
50
nCDC_DWN_RST
50
SMSC LPC47M182
199
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET