Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
t1
t2
t3
nWRITE
PD<7:0>
t4
t5
t6
t7
nDATASTB
nADDRSTB
t8
t9
nWAIT
Figure 13.13 – EPP 1.9 Data Or Address Write Cycle
NAME
t1
t2
t3
t4
DESCRIPTION
MIN
60
60
0
10
5
TYP
MAX
185
185
UNITS
ns
ns
ns
ns
nWAIT Asserted to nWRITE Asserted (Note 1)
nWAIT Asserted to nWRITE Change (Note 1)
nWAIT Asserted to PDATA Invalid (Note 1)
PDATA Valid to Command Asserted
nWRITE to Command Asserted
t5
35
ns
t6
t7
nWAIT Asserted to Command Asserted (Note 1)
nWAIT Deasserted to Command Deasserted
(Note 1)
60
60
210
190
ns
ns
t8
t9
Command Asserted to nWAIT Deasserted
Command Deasserted to nWAIT Asserted
0
0
10
us
ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered to have
settled after it does not transition for a minimum of 50 nsec.
SMSC LPC47M182
205
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
