Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
t1
t2
nWRITE
PD<7:0>
t3
t4
nDATASTB
nADDRSTB
t5
nWAIT
Figure 13.15 – EPP 1.7 Data Or Address Write Cycle
NAME
DESCRIPTION
Command Deasserted to nWRITE Change
Command Deasserted to PDATA Invalid
PDATA Valid to Command Asserted
nWRITE to Command
MIN
0
50
10
5
TYP
MAX
40
UNITS
ns
ns
ns
ns
t1
t2
t3
t4
t5
35
35
Command Deasserted to nWAIT Deasserted
0
ns
nWRITE
t1
t2
PD<7:0>
nDATASTB
nADDRSTB
t3
nWAIT
Figure 13.16 – EPP 1.7 Data Or Address Read Cycle
NAME
DESCRIPTION
MIN
0
0
TYP
MAX
UNITS
ns
ns
t1
t2
t3
Command Asserted to PDATA Valid
Command Deasserted to PDATA Hi-Z
Command Deasserted to nWAIT Deasserted
0
ns
SMSC LPC47M182
207
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
