Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
CLK
t1
Output Delay
t2
t3
Tri-State Output
Figure 13.5 - Ouput Timing Measurement Conditions, LPC Signals
NAME
DESCRIPTION
CLK to Signal Valid Delay – Bused Signals
Float to Active Delay
MIN
2
2
TYP
MAX
11
11
UNITS
ns
ns
t1
t2
t3
Active to Float Delay
28
ns
t1
t2
CLK
Inputs Valid
Input
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals
NAME
t1
t2
DESCRIPTION
Input Set Up Time to CLK – Bused Signals
Input Hold Time from CLK
MIN
7
0
TYP
MAX
UNITS
ns
ns
PCI_CLK
nLFRAME
LAD[3:0]
L1 L2
Address
Data
TAR
Sync=0110
L3
TAR
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
Figure 13.7 - I/O Write
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
202
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
