Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 8 Power Control Runtime Registers
Table 8.1 shows the runtime registers summary in the Power Control logical Device. Table 8.2 shows the
runtime registers description in the Power Control logical device. These runtime registers can only be
accessed when LD_NUM bit in the TEST 7 configuration register is ‘0’ (see Table 11.3). The register
offsets are from the base address programmed in the Power Control logical device.
Table 8.1 – Power Control Runtime Registers Summary, LD_NUM Bit = 0
REGISTER
SOFT
TYPE
PCI Reset
VCC POR VTR POR
REGISTER
OFFSET
(hex)
RESET
00
01 – 03
04
05 – 07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
R/W
R
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PME_STS
Reserved – reads return 0
PME_EN
Reserved – reads return 0
PME_STS3
PME_STS2
PME_STS1
-
-
0x00
-
-
-
-
-
0x00
0x00
0x00
-
Reserved – reads return 0
PME_EN3
-
-
-
-
0x00
0x00
0x00
-
PME_EN2
PME_EN1
Reserved – reads return 0
LED
Keyboard Scan Code
Tach1 LSB
-
-
-
-
-
-
-
-
0x03
0x00
0x00
0x00
0x00
0x00
0x80
0x00
-
Tach1 MSB
-
-
-
-
Tach2 LSB
R
Tach2 MSB
nIO_PME Register
MSC_STS
Force Disk Change
Floppy Data Rate Select Shadow
UART1 FIFO Control Shadow
Interrupt Generating Register 1
Interrupt Generating Register 2
UART2 FIFO Control Shadow
Reserved – reads return 0
R/W
R/W
R/W
R
0x01
-
-
0xFF
0xFF
-
-
0x01
-
-
R
-
-
R/W
R/W
R
0xFF
-
0xFF
-
1D
1E-1F
-
-
-
-
R
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
154
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
