Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
power. The polarity bit will affect the output and input to the CNR logic. The output type select bit will
also affect the GP24 pin.
If GP24 is programmed as GPIO input, it will not affect the nCDC_DWN_ENAB input into the CNR
logic. It will function as a normal GPIO input and can be used as a PME event.
Table 7.49 – CNR Logic Truth Table
INPUTS
OUTPUT
NCDC_DWN_ENAB
NAUD_LNK_RST
nCDC_DWN_RST
(NOTE)
0
0
1
1
0
1
0
1
0
0
1
0
Note:
If GP24 is programmed as GPIO output the GP data bit will also control nCDC_DWN_ENAB input to the
CNR logic.
This follows the boolean equation:
(nAUD_LNK_RST)x( nCDC_DWN_ENAB )=nCDC_DWN_RST
SMSC I/O
nAUD_LNK_RST
nCDC_DWN_RST
nCDC_DWN
_ENAB
10k
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Figure 7.19 – CNR Circuit
See Table 13.6 for CNR timing.
SMSC LPC47M182
153
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
