Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 7.14 – Keyboard Port 92 Register
NAME
Location
Default Value
Attribute
Size
PORT 92
92h
24h
Read/Write
8 bits
PORT 92 REGISTER
BIT
7:6
5
4
3
FUNCTION
Reserved. Returns 00 when read
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
2
1
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be
driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.
0
Alternate System Reset. This read/write bit provides an alternate system reset
function. This function provides an alternate means to reset the system CPU to
effect a mode switch from Protected Virtual Address Mode to the Real Address
Mode. This provides a faster means of reset than is provided by the Keyboard
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause
the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of
500 ns. Before another nALT_RST pulse can be generated, this bit must be written
back to a 0.
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control.
This signal is AND’ed together with the reset signal (KRST) from the keyboard controller to provide a
software means of resetting the CPU. This provides a faster means of reset than is provided by the
keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a
minimum of 6µs, after a delay of a minimum of 14µs. Before another nALT_RST pulse can be generated,
bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven
inactive high (bit 0 in the Port 92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0
of the Port 92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is
output on pin nKBDRST and its polarity is controlled by the GPI/O polarity configuration.
SMSC LPC47M182
123
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
