REG OFFSET
(hex)
NAME
DESCRIPTION
General Purpose I/0 bit 4.3
GP43
3E
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Either Edge Triggered Interrupt Input 3
10=Reserved
Default = 0x01
on VTR POR
(R/W)
Bits[3:2] are reset
(cleared) on VCC
POR, VTR POR and
PCI Reset
01=Device Disable Register Control. The GP43 pin is an input,
with non-inverted polarity. When bits[3:2]=01, they cannot be
changed by writing to these bits; they are cleared by VCC POR,
PCI Reset and VTR POR. That is, when the DDRC function is
selected for this pin, it cannot be changed, except by a VCC POR,
PCI Reset or VTR POR.
The Device Disable register is controlled by the value of the GP43
pin as follows:
If the GP43 pin is high, the Device Disable Register is Read-Only.
If the GP43 pin is low, the Device Disable Register is Read/Write.
00=Basic GPIO function
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP50
3F
General Purpose I/0 bit 5.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= RI2# (User Note 1)
0=GPIO
Default = 0x01
on VTR POR
(R/W)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP51
40
General Purpose I/0 bit 5.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDCD2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP52
41
General Purpose I/0 bit 5.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Reserved
Default = 0x01
on VTR POR
(R/W)
10=IRRX (Note 6)
01=RXD2 (Note 6)
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
SMSC LPC47S45x
Page 178 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
