In polled applications, the PIN bit is tested to determine when a serial transmission/reception has been completed.
When the ENI bit (bit 4 of write-only section of the control/status register) is also set to logic “1” the hardware interrupt
is enabled. In this case, the PI flag also triggers and internal interrupt (active low) via the nINT output each time PIN
is reset to logic “0”.
When acting as a slave transmitter or slave receiver, while PIN = “0”, the chip will suspend SMBus transmission by
holding the SCLK line low until the PIN bit is set to logic “1” (inactive). This prevents further data from being
transmitted or received until the current data byte in the data register has been read (when acting as slave receiver)
or the next data byte is written to the data register (when acting as slave transmitter).
PIN Bit Summary
The PIN bit can be used in polled applications to test when a serial transmission has been completed. When the ENI
bit is also set, the PIN flag sets the internal interrupt via the nINT output.
In transmitter mode, after successful transmission of one byte on the SMBus the PIN bit will be automatically reset to
logic “0” (active) indicating a complete byte transmission.
In transmitter mode, PIN is set to logic “1” (inactive) each time the data register is written.
In receiver mode, PIN is set to logic “0” (inactive) on completion of each received byte.
Subsequently, the SCLK line will be held low until PIN is set to logic “1”.
In receiver mode, when the data register is read, PIN is set to logic “1” (inactive).
In slave receiver mode, an SMBus STOP condition will set PIN=0 (active).
PIN=0 if a bus error (BER) or a timeout error (TE) occurs while the Timeout Interrupt Enable is asserted (TIE).
Bit 6 TE
When the Timeout Error bit D6 is ‘1’, an SMBus timeout error has occurred (see Section 0 SMBus Timeout).
Timeout errors generate an interrupt if the TIE bit is asserted (see Section on Bit 4 TIE). If the TIE bit is asserted,
timeout errors will assert the PIN bit.
The TE bit is deasserted ‘0’ whenever the PIN bit is deasserted (see Section on Bit 7 Pin).
Bit 5 STS
When in slave receiver mode, this flag is asserted when an externally generated STOP condition is detected (used
only in slave receiver mode).
Bit 4 BER
Bus error; a misplaced START or STOP condition has been detected. Resets nBB (to logic “1”; inactive), sets PIN =
“0” (active).
Bit 3 LRB/AD0
Last Received Bit or Address 0 (general call) bit. This status bit serves a dual function, and is valid only while PIN=0:
LRB holds the value of the last received bit over the SMBus while AAS=0 (not addressed as slave). Normally
this will be the value of the slave acknowledgment; thus checking for slave acknowledgment is done via testing
of the LRB.
ADO; when AAS = “1” (Addressed as slave condition) the SMBus controller has been addressed as a slave.
Under this condition, this bit becomes the AD0 bit and will be set to logic “1” if the slave address received was
the ‘general call’ (00h) address, or logic “0” if it was the SMBus controller’s own slave address.
Bit 2 AAS
Addressed As Slave bit. Valid only when PIN=0. When acting as slave receiver, this flag is set when an incoming
address over the SMBus matches the value in own address register (shifted by one bit) or if the SMBus ‘general call’
address (00h) has been received (‘general call’ is indicated when AD0 status bit is also set to logic “1”).
Bit 1 LAB
Lost Arbitration Bit. This bit is set when, in multi-master operation, arbitration is lost to another master on the SMBus.
SMSC LPC47S45x
Page 132 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
