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LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LPC47M10X_07的Datasheet PDF文件第102页浏览型号LPC47M10X_07的Datasheet PDF文件第103页浏览型号LPC47M10X_07的Datasheet PDF文件第104页浏览型号LPC47M10X_07的Datasheet PDF文件第105页浏览型号LPC47M10X_07的Datasheet PDF文件第107页浏览型号LPC47M10X_07的Datasheet PDF文件第108页浏览型号LPC47M10X_07的Datasheet PDF文件第109页浏览型号LPC47M10X_07的Datasheet PDF文件第110页  
GPIO PME and SMI Functionality  
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable  
registers:  
GP10-GP17  
GP20-GP22, GP24-GP27  
GP30-GP33  
GP41, GP43  
GP50-GP57  
GP60, GP61  
The following PME status and enable registers for these GPIOs:  
PME_STS2 and PME_EN2 for GP10-GP17  
PME_STS3 and PME_EN3 for GP20-GP22, GP24-GP27  
PME_STS4 and PME_EN4 for GP30-GP33, GP41, GP43, GP60 and GP61  
PME_STS5 and PME_EN5 for GP50-GP57  
The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable  
registers.  
GP20-GP22, GP24-GP26  
GP30-GP33  
GP41, GP42, GP43  
GP54-GP57  
GP60, GP61  
The following SMI status and enable registers for these GPIOs:  
SMI_STS3 and SMI_EN3 for GP20-GP22, GP24-GP26 and GP60  
SMI_STS4 and SMI_EN4 for GP30-GP33, GP41, GP42, GP43 and GP61  
SMI_STS5 and SMI_EN5 for GP54-GP57, FAN_TACH1 and FAN_TACH2.  
The following GPIOs have “either edge triggered interrupt” (EETI) input capability. These GPIOs can generate a  
PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in  
the MSC_STS status register that is set on both edges. The corresponding bits in the PME and SMI status registers  
are also set on both edges.  
GP21, GP22  
GP41, GP43  
GP60, GP61  
The following table summarizes the PME and SMI functionality for each GPIO. It also shows the Either Edge  
Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on the I/O pads.  
BUFFER  
GPIO  
GP10-GP17  
GP20-GP22, GP24-GP26  
GP27  
GP30, GP31  
GP32, GP33  
GP35  
GP36, GP37  
GP40  
GP41  
GP42  
GP43  
GP50-GP52  
GP53  
PME  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
No  
No  
SMI  
No  
EETI  
POWER  
VCC  
VCC  
VCC  
VCC  
VCC  
VTR  
VCC  
VCC  
VCC  
VTR  
VCC  
VCC  
VTR  
VCC  
VTR  
NOTES  
No  
GP21, GP22  
No  
4
4
4
4
5
1
2
2
4
Yes  
nIO_SMI  
Yes  
Yes  
No  
No  
No  
No  
No  
No  
Yes  
No  
Yes  
No  
No  
No  
No  
Yes  
Yes  
Yes  
No  
No  
Yes  
Yes  
Yes  
nIO_PME  
Yes  
4, 6  
4
1, 5  
4
Yes  
Yes  
Yes  
Yes  
GP54-GP57  
GP60, GP61  
No  
Yes  
3, 4  
Note 1: GP35 and GP53 have the IRTX function and their output buffers are powered by VTR so that the pins are  
always forced low when not used.  
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